The present invention relates to a semiconductor integrated circuit device having control signal generating circuits.
Owing to the advanced integrated circuit technology, the number of functions implemented with an integrated circuit chip is increasing. In many cases, part of the functions performed by a chip need to be always active and others are required to be active only when they are called upon. However, power is always supplied to all parts of conventional semiconductor integrated circuit devices of this nature.
One example of such semiconductor integrated circuit devices is a random access memory having the fault tolerant function, and it is provided with spare memory circuits in addition to primary memory circuits within a chip. When a faulty bit is in the primary memory circuit, the faulty bit portion is replaced with one from a spare memory circuit, so that the number of useful bits in the memory are not reduced. On the other hand, when there is no faulty bit in primary memory circuits, it is sufficient to operate only the primary memory circuit. However, extra power is wasted in order to keep the spare memory circuit active in conventional devices of this nature. One example of such arrangement is disclosed in an article entitled "A 1 Mb Full Wafer MOS RAM", by Y. Egawa, ISSCC Digest of Technical Papers, Feb. 14, 1979, pages 18-19.
In order to obviate the probem of wasted power as noted above, it has been proposed to interrupt the power line of a spare memory circuit by burning with a laser when it is not necessary to use the spare circuit. Such technology is disclosed in an article entitled "Fault Tolerant 92160 Bit Multiphase CCD Memory", by B. R. Elmer et al., ISSCC Digest of Technical Papers, Feb. 17, 1977, pages 116-117. In this method, however, the laser beam for burning the power line of a spare memory circuit adversely may affect other components included in the same chip, resulting in poor reliability of the device. Moreover, burning the power line by use of a laser needs a special work shop, skilled manpower and considerable time, making difficult real time final inspection of chips and thus limiting the speed of manufacturing. Furthermore, this method involves other problems. For example, the spare memory circuit cannot be activated after the chip has been sealed in a package. Further, the process needs laser burning equipment which ordinarily is not used in LSI circuit testing.